FIG. 1 is a schematic diagram of a GaAs metal-semiconductor field effect transistor (MESFET) having a double recess channel with an N+ ledge structure. An N+ ledge structure transistor includes raised N+ source and drain regions above an N channel region with the source and drain contacts set back from the edge of the source and drain regions near the recess for the channel region. Epitaxial layer 3 is formed by epitaxial deposition of GaAs onto substrate 1 and buffer layer 2. Source/drain regions 4 are formed by epitaxial deposition of N+ GaAs on the surface of epitaxial layer 3 and etching a wide recess through the epitaxial layer 4 to epitaxial layer 3. This structure may also be formed using ion implantation processes. Gate contact 14, source contact 15 and drain contact 16 are formed using techniques well known in the art. This structure has been shown to have increased resistance to both instantaneous and long-term burnout (see Wemple, Niehaus, Fukui, Irvin, Cox, Hwang, DiLorenzo, and Schlosser, "Long-term and Instantaneous Burnout in GaAs Power FET'S: Mechanisms and Solutions", IEEE Transactions on Electron Devices, Volume ED-28, 834 (July 1981 )), and has shown improved performance over conventional field effect transistors (FETs) as power FETs in the microwave range (see Saunier and Shih, "High-Performance K-Band GaAs Power Field-Effect Transistors Prepared By Molecular Beam Epitaxy", Applied Physics Letters, Volume 42, 966 (1 June 1983)).
However, prior processes for fabricating double recess FETs with N+ ledges require two critical masking steps. FIGS. 2A through 2C are schematic diagrams depicting the processing steps necessary to fabricate a double recess, N+ ledge field effect transistor according to the prior art. N+ layer 4 of FIG. 2A is deposited on epitaxial layer 3 by, for example, molecular beam epitaxy, and source contact 16 and drain contact 15 are formed on the surface of N+ layer 4. Photoresist layer 17 is formed and patterned on the surface of N+ layer 4 using techniques well known in the art. Epitaxial layer 4 and a small part of epitaxial layer 3 are then etched using techniques well known in the art and photoresist layer 17 is removed to provide wide recess 21 shown in FIG. 2B. Photoresist layer 18 is then formed and patterned on the surface of N+ layer 4 using techniques well known in the art. N layer 3 is then etched using techniques well known in the art down to the final thickness to provide the structure shown in FIG. 2C. Gate metal contact 14 is then formed on the structure of FIG. 2C and photoresist layer 18 is removed to provide the structure of FIG. 1. Of importance, the process described with reference to FIG. 1 and FIGS. 2A through 2C requires two critical masking steps; these are: patterning photoresist layer 17 and patterning photoresist layer 18. Both of these masking steps must be properly aligned for the transistor to operate properly. As is well known in the art, each masking step introduces additional probability of error in the fabrication of a semiconductor device in an integrated circuit. Thus it is desirable to minimize the number of masking steps used to fabricate a double recess, N+ ledge FET.